The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes

摘要

Internet-of-Things end-nodes demand low power processing platformscharacterized by heterogeneous dedicated units, controlled by a processor corerunning concurrent control threads. Such architecture scheme fits one of themain target application domain of the RISC-V instruction set. We present anopen-source processing core compliant with RISC-V on the software side and withthe popular Pulpino processor platform on the hardware side, while supportinginterleaved multi-threading for IoT applications. The latter feature is a novelcontribution in this application domain. We report details about themicroarchitecture design along with performance data.